1. Field of the Invention
The invention relates to a semiconductor device fabricated in a size which is approximately the same as that of a semiconductor element, and also relates to a connecting substrate used in such a semiconductor device and a method of manufacturing the connecting device.
2. Description of the Related Art
A chip sized package (CSP) is a semiconductor device fabricated in a size which is approximately the same as that of a semiconductor element, and is provided on its mounting face with external connection terminals such as solder bumps so as to be capable of being mounted on a mounting substrate by use of the external connection terminals. In general, external connection terminals are arranged, in an array, on a mounting face of a chip sized package to cope with multi-pin arrangement required of advanced semiconductor devices.
FIG. 7 illustrates an example in which terminals 14 to be subsequently connected with external connection terminals are arranged on a mounting face of a semiconductor element 10. In the drawing, electrodes formed on the mounting face of the semiconductor element 10 are designated by reference numeral 12, and patterned wirings for the connection between the electrodes 12 and the terminals 14 are designated by 16.
The terminals 14 are arranged in an array on the face, on which electrode terminals are formed, of the semiconductor element 10 by, for example, a method in which, as shown in FIG. 8, the patterned wirings 16 are rerouted on the surface of a passivation film 8 of the semiconductor element 10, and the terminal 14 is provided at an end of the patterned wiring 16, or a method in which a wiring patterned film having terminals provided in a given arrangement is bonded to the electrode/terminal-formed face of the semiconductor element through a buffer layer. The patterned wirings 16 are located on an insulation film formed on the passivation film 8, although the insulation film is not shown in FIG. 8.
The electrode terminal 14 to be connected with the external connection terminal 26 (FIG. 8) is required to have a diameter of an order of 300 micrometers. Accordingly, if the terminals 14 are positioned directly on electrode/terminal-formed face of the semiconductor element 10, the distance between adjacent terminals 14 is narrower, and the space where the patterned wirings 16 are arranged is restricted. Arranging the electrodes 12 at a higher density to increase the number of electrodes 12 results in an increase in the number of patterned wirings 16 connecting the electrodes 12 to the terminals 14, which makes it more difficult to obtain the space where the patterned wirings 16 are rerouted.
Although it is envisaged that the patterned wirings 16 are formed in multiple layers when the patterned wirings 16 cannot be rerouted within the electrode/terminal-formed face of the semiconductor element 10, forming the patterned wirings 16 in multiple layers raises problems with respect to a complicated manufacturing process and reliability of products.
Also, when the buffer layer and wiring patterned film were used as interposers to electrically connect the electrodes 12 of the semiconductor element 10 to the terminals provided on the wiring patterned film, there were problems of complexities of a process for the manufacture of the wiring patterned film and operations for the manufacture of semiconductor devices.